jaulib v1.3.6
Jau Support Library (C++, Java, ..)
Loading...
Searching...
No Matches
cpuid.hpp
Go to the documentation of this file.
1/*
2 * Author: Sven Gothel <sgothel@jausoft.com>
3 * Copyright (c) 2022 Gothel Software e.K.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef JAU_CPUID_HPP_
26#define JAU_CPUID_HPP_
27
28#include <jau/byte_util.hpp>
29#include <jau/enum_util.hpp>
30#include <string>
31
32namespace jau::cpu {
33
34 using namespace jau::enums;
35
36 /** \addtogroup SysUtils
37 *
38 * @{
39 */
40
41 /**
42 * Returns the compile time pointer architecture size in bits.
43 * e.g. 64-bit for LP64 and 32-bit for LP32.
44 *
45 * Implementations uses `sizeof(void*)`, i.e. the address bus size,
46 * the common denominator across all LP64, ILP64 and LLP64 for 64-bit.
47 */
48 constexpr size_t pointer_bit_size() noexcept { return sizeof(void*) * 8; }
49
50 enum class cpu_family_t : uint16_t {
51 /** Undefined */
52 none = 0,
53
54 /** ARM 32bit */
55 arm32 = 1,
56 /** ARM 64bit */
57 arm64 = 2,
58
59 /** AMD/Intel 32-bit */
60 x86_32 = 10,
61 /** AMD/Intel 64-bit */
62 x86_64 = 11,
63 /** Itanium */
64 ia64 = 12,
65
66 /** Power PC 32bit */
67 ppc32 = 20,
68 /** Power PC 32bit */
69 ppc64 = 21,
70
71 /** SPARC 32bit */
72 sparc32 = 30,
73 /** SPARC 32bit */
74 sparc64 = 31,
75
76 /** Mips 32bit */
77 mips32 = 40,
78 /** Mips 64bit */
79 mips64 = 41,
80
81 /** Hitachi SuperH 32bit */
83 /** Hitachi SuperH 64bit */
85
86 /** WebAssembly 32-bit */
87 wasm32 = 60,
88 /** WebAssembly 64-bit */
89 wasm64 = 61
90
91 };
93
94 enum class arm32_hwcap1_t : uint64_t {
95 none = 0,
96 swp = (1 << 0),
97 half = (1 << 1),
98 thumb = (1 << 2),
99 bits26 = (1 << 3),
100 fmult = (1 << 4),
101 fpa = (1 << 5),
102 vfp = (1 << 6),
103 edsp = (1 << 7),
104 java = (1 << 8),
105 iwmmxt = (1 << 9),
106 crunch = (1 << 10),
107 thumbee = (1 << 11),
108 neon = (1 << 12),
109 vfp_v3 = (1 << 13),
110 vfp_v3_d16 = (1 << 14),
111 tls = (1 << 15),
112 vfp_v4 = (1 << 16),
113 idiva = (1 << 17),
114 idivt = (1 << 18),
115 vfp_d32 = (1 << 19),
116 lpae = (1 << 20),
117 evtstrm = (1 << 21),
118
120 };
124
125 enum class arm32_hwcap2_t : uint64_t {
126 none = 0,
127 aes = (1 << 0),
128 pmull = (1 << 1),
129 sha1 = (1 << 2),
130 sha2 = (1 << 3),
131 crc32 = (1 << 4),
132
134 };
136
137 enum class arm64_hwcap_t : uint64_t {
138 none = 0,
139 fp = (1 << 0),
140 asimd = (1 << 1),
141 evtstrm = (1 << 2),
142 aes = (1 << 3),
143 pmull = (1 << 4),
144 sha1 = (1 << 5),
145 sha2 = (1 << 6),
146 crc32 = (1 << 7),
147 atomics = (1 << 8),
148 fphp = (1 << 9),
149 asimdhp = (1 << 10),
150 cpuid = (1 << 11),
151 asimdrdm = (1 << 12),
152 jscvt = (1 << 13),
153 fcma = (1 << 14),
154 lrcpc = (1 << 15),
155 dcpop = (1 << 16),
156 sha3 = (1 << 17),
157 sm3 = (1 << 18),
158 sm4 = (1 << 19),
159 asimddp = (1 << 20),
160 sha512 = (1 << 21),
161 sve = (1 << 22),
162 asimdfhm = (1 << 23),
163 dit = (1 << 24),
164 uscat = (1 << 25),
165 ilrcpc = (1 << 26),
166 flagm = (1 << 27),
167 ssbs = (1 << 28),
168 sb = (1 << 29),
169 paca = (1 << 30),
170 pacg = (1UL << 31),
171
173 };
177
178 /** Singleton CpuInfo caching all jau::cpu information */
179 class CpuInfo {
180 public:
181 /** See pointer_bit_size() */
183 /** Size of a page in bytes or zero if not available */
184 size_t page_size;
185 /** True if successfully queried l1_share_max and l1_apart_min. */
187 /** Maximum size of contiguous memory to promote true sharing if has_l1_minmax, or zero */
189 /** Minimum offset between two objects to avoid false sharing if has_l1_minmax, or zero */
191 /** Number of available concurrent threads (cores) or zero if information is not available, using C++11 std::thread::hardware_concurrency() */
193 /** Number of available/online cores from system call */
195 /** Number of installed/configured cores from system call */
197 /** cpu_family_t derived from [Architectures](https://sourceforge.net/p/predef/wiki/Architectures/) predefined compiler macros. */
200 /** True if successfully queried arm32_hwcap1 and arm32_hwcap1 on cpu_family_t::arm32. */
202 /** arm32_hwcap1_t info if available, i.e. has_arm32_hwcap */
204 /** arm32_hwcap2_t info if available, i.e. has_arm32_hwcap */
206 /** True if successfully queried arm64_hwcap on cpu_family_t::arm64. */
208 /** arm64_hwcap_t info if available, i.e. has_arm64_hwcap */
210
211 private:
212 CpuInfo() noexcept;
213
214 public:
215 CpuInfo(const CpuInfo&) = delete;
216 void operator=(const CpuInfo&) = delete;
217
218 /** Returns reference to const singleton instance */
219 static inline const CpuInfo& get() noexcept {
220 static CpuInfo ci;
221 return ci;
222 }
223
224 /** Returns maximum number of available/online cores, i.e. max(sys_online_cores, concurrent_threads). */
225 inline size_t online_core_count() const noexcept {
226 return std::max(sys_online_cores, concurrent_threads);
227 }
228
229 std::string toString(std::string& sb, bool details_only=false) const noexcept;
230 std::string toString() const noexcept {
231 std::string sb; toString(sb); return sb;
232 }
233 };
234
235 inline std::string get_cpu_info(std::string& sb) noexcept {
236 return CpuInfo::get().toString(sb);
237 }
238 inline std::string get_cpu_info() noexcept {
239 std::string sb; CpuInfo::get().toString(sb); return sb;
240 }
241
242 /**@}*/
243
244} // namespace jau::cpu
245
246#endif /* JAU_CPUID_HPP_ */
247
size_t pointer_bits
See pointer_bit_size()
Definition cpuid.hpp:182
size_t sys_online_cores
Number of available/online cores from system call.
Definition cpuid.hpp:194
static const CpuInfo & get() noexcept
Returns reference to const singleton instance.
Definition cpuid.hpp:219
std::string toString() const noexcept
Definition cpuid.hpp:230
size_t l1_apart_min
Minimum offset between two objects to avoid false sharing if has_l1_minmax, or zero.
Definition cpuid.hpp:190
size_t online_core_count() const noexcept
Returns maximum number of available/online cores, i.e.
Definition cpuid.hpp:225
cpu_family_t family
cpu_family_t derived from Architectures predefined compiler macros.
Definition cpuid.hpp:198
bool has_l1_minmax
True if successfully queried l1_share_max and l1_apart_min.
Definition cpuid.hpp:186
arm32_hwcap1_t arm32_hwcap1
arm32_hwcap1_t info if available, i.e.
Definition cpuid.hpp:203
std::string toString(std::string &sb, bool details_only=false) const noexcept
Definition cpuid.cpp:275
bool has_arm32_hwcap
True if successfully queried arm32_hwcap1 and arm32_hwcap1 on cpu_family_t::arm32.
Definition cpuid.hpp:201
size_t sys_max_cores
Number of installed/configured cores from system call.
Definition cpuid.hpp:196
size_t page_size
Size of a page in bytes or zero if not available.
Definition cpuid.hpp:184
jau::endian_t byte_order
Definition cpuid.hpp:199
arm64_hwcap_t arm64_hwcap
arm64_hwcap_t info if available, i.e.
Definition cpuid.hpp:209
size_t l1_share_max
Maximum size of contiguous memory to promote true sharing if has_l1_minmax, or zero.
Definition cpuid.hpp:188
bool has_arm64_hwcap
True if successfully queried arm64_hwcap on cpu_family_t::arm64.
Definition cpuid.hpp:207
arm32_hwcap2_t arm32_hwcap2
arm32_hwcap2_t info if available, i.e.
Definition cpuid.hpp:205
size_t concurrent_threads
Number of available concurrent threads (cores) or zero if information is not available,...
Definition cpuid.hpp:192
endian_t
Endian identifier, indicating endianess of all scalar types.
#define JAU_MAKE_ENUM_STRING(type,...)
#define JAU_MAKE_BITFIELD_ENUM_STRING(type,...)
arm32_hwcap2_t
Definition cpuid.hpp:125
arm64_hwcap_t
Definition cpuid.hpp:137
constexpr size_t pointer_bit_size() noexcept
Returns the compile time pointer architecture size in bits.
Definition cpuid.hpp:48
std::string get_cpu_info() noexcept
Definition cpuid.hpp:238
cpu_family_t
Definition cpuid.hpp:50
arm32_hwcap1_t
Definition cpuid.hpp:94
@ x86_64
AMD/Intel 64-bit.
Definition cpuid.hpp:62
@ none
Undefined.
Definition cpuid.hpp:52
@ arm64
ARM 64bit.
Definition cpuid.hpp:57
@ x86_32
AMD/Intel 32-bit.
Definition cpuid.hpp:60
@ sparc32
SPARC 32bit.
Definition cpuid.hpp:72
@ wasm64
WebAssembly 64-bit.
Definition cpuid.hpp:89
@ superh32
Hitachi SuperH 32bit.
Definition cpuid.hpp:82
@ superh64
Hitachi SuperH 64bit.
Definition cpuid.hpp:84
@ arm32
ARM 32bit.
Definition cpuid.hpp:55
@ wasm32
WebAssembly 32-bit.
Definition cpuid.hpp:87
@ ppc64
Power PC 32bit.
Definition cpuid.hpp:69
@ mips64
Mips 64bit.
Definition cpuid.hpp:79
@ sparc64
SPARC 32bit.
Definition cpuid.hpp:74
@ mips32
Mips 32bit.
Definition cpuid.hpp:77
@ ppc32
Power PC 32bit.
Definition cpuid.hpp:67
Author: Sven Gothel sgothel@jausoft.com Copyright Gothel Software e.K.
Definition enum_util.hpp:65
STL namespace.